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51
PRELIMINARY
CY7C027/028 CY7C037/038
32K/64K x 16/18 Dual-Port Static RAM
Features
* True Dual-Ported memory cells which allow simultaneous access of the same memory location * 32K x 16 organization (CY7C027) * 64K x 16 organization (CY7C028) * 32K x 18 organization (CY7C037) * 64K x 18 organization (CY7C038) * 0.35-micron CMOS for optimum speed/power * High-speed access: 12[1]/15/20 ns * Low operating power -- Active: ICC = 180 mA (typical) -- Standby: ISB3 = 0.05 mA (typical) * Fully asynchronous operation * Automatic power-down * Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device * On-chip arbitration logic * Semaphores included to permit software handshaking between ports * INT flags for port-to-port communication * Separate upper-byte and lower-byte control * Dual Chip Enables * Pin select for Master or Slave * Commercial and industrial temperature ranges * Available in 100-pin TQFP * Pin-compatible and functionally equivalent to IDT7027
Logic Block Diagram
R/WL UBL R/WR UBR
CE0L CE1L LBL OEL
CEL
CER
CE0R CE1R LBR OE R
[2]
8/9 8/9
8/9
[2]
I/O 8/9L-I/O 15/17L
[3]
I/O 0L-I/O 7/8L
I/O Control
I/O Control
8/9
I/O8/9L-I/O 15/17R
[3]
I/O0L-I/O7/8R
A0L-A14/15L
[4]
15/16
Address Decode
15/16
True Dual-Ported RAM Array
Address Decode
15/16
15/16
A0R-A 14/15R
[4]
[4]
[4]
A0L-A14/15L CEL OEL R/WL SEM L BUSYL INTL UBL LBL
[5]
Interrupt Semaphore Arbitration
A0R-A 14/15R CER OE R R/WR SEM R
[5]
M/S
4. 5.
BUSY R INT R UBR LB R
A0-A14 for 32K; A0-A15 for 64K devices. BUSY is an output in master mode and an input in slave mode.
Notes: 1. See page 6 for Load Conditions. 2. I/O8-I/O15 for x16 devices; I/O9-I/O17 for x18 devices. 3. I/O0-I/O7 for x16 devices; I/O0-I/O8 for x18 devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 November 23, 1998
PRELIMINARY
Functional Description
The CY7C027/028 and CY7C037/038 are low-power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.
CY7C027/028 CY7C037/038
Each port has independent control pins: dual chip enables (CE0 and CE1), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by the chip enable pins. The CY7C027/028 and CY7C037/038 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
BUSYL BUSYR GND INTR INTL A0R A1R A2R A3R A4R A5R A6R A7R A8R 75 74 73 72 71 70 69 68 67 66 65 M/S A8L A7L A6L A5L A4L A3L A2L A1L A0L NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L A14L [Note 6] A15L NC NC LBL UBL CE0L CE1L SEML VCC R/WL OEL GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A9R A10R A11R A12R A13R A14R A15R [Note 6] NC NC LBR UBR CE0R CE1R SEMR GND R/WR OER GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
CY7C028 (64K x 16) CY7C027 (32K x 16)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
VCC
GND
GND
I/01R
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Note: 6. This pin is NC for CY7C027.
I/O0L
2
NC
PRELIMINARY
Pin Configurations (continued)
100-Pin TQFP (Top View)
BUSYR BUSYL GND INTL INTR GND VCC A0R A1R A2R A3R A4R A5R A6R A7R A8L A7L A6L A5L A4L A3L A2L A1L A0L M/S
CY7C027/028 CY7C037/038
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L A14L [Note 7] A15L LBL UBL CE0L CE1L SEML R/WL OEL VCC GND I/O17L I/O16L GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 A8R A9R A10R A11R A12R A13R A14R A15R [Note 7] LBR UBR CE0R CE1R SEMR R/WR GND OER GND I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
CY7C038 (64K x 18) CY7C037 (32K x 18)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
VCC
GND
GND
I/01R
VCC
Selection Guide
CY7C027/028 CY7C037/038 -12[1] Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for ISB1 (mA) (Both ports TTL level) Typical Standby Current for ISB3 (mA) (Both ports CMOS level)
Note: 7. This pin is NC for CY7C037.
CY7C027/028 CY7C037/038 -15 15 190 50 0.05
I/O10R
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
CY7C027/028 CY7C037/038 -20 20 180 45 0.05
12 195 55 0.05
3
PRELIMINARY
Pin Definitions
Left Port CE0L, CE1L R/WL OEL A0L-A15L I/O0L-I/O 17L SEML UBL LBL INTL BUSYL M/S VCC GND NC R/WR OER A0R-A15R I/O0R-I/O 17R SEMR UBR LBR INTR BUSYR Right Port CE0R, CE1R Description
CY7C027/028 CY7C037/038
Chip Enable (CE is LOW when CE0 VIL and CE1 VIH) Read/Write Enable Output Enable Address (A0-A14 for 32K; A0-A15 for 64K devices) Data Bus Input/Output (I/O0-I/O15 for x16 devices; I/O0-I/O17 for x18) Semaphore Enable Upper Byte Select (I/O8-I/O 15 for x16 devices; I/O9-I/O 17 for x18 devices) Lower Byte Select (I/O0-I/O 7 for x16 devices; I/O0-I/O 8 for x18 devices) Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >1100V Latch-Up Current.................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied .............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................ -0.5V to +7.0DC Input Voltage[8] ............................................... -0.5V to +7.0V
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Shaded area contains advance information.
Note: 8. Pulse width < 20 ns.
4
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY7C027/028 CY7C037/038 -12[1] Symbol VOH VOL VIH VIL IOZ ICC Parameter Output HIGH Voltage (VCC=5V) Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (V CC=Max, IOUT=0 mA) Outputs Disabled Com'l. Indust. 55 75 -10 195 2.2 0.8 10 325 -10 190 215 50 65 125 205 120 135 0.05 0.25 0.05 0.05 115 185 110 125 Min 2.4 0.4 2.2 0.8 10 280 305 70 95 180 205 0.25 0.25 160 175 -10 Typ Max Min 2.4 0.4 2.2 -15 Typ Max Min 2.4
CY7C027/028 CY7C037/038
-20 Typ Max 0.4 0.8 10 180 305 45 60 110 125 0.05 0.05 100 115 265 290 65 80 160 175 0.25 0.25 140 155 Units V V V V A mA mA mA mA mA mA mA mA mA mA
ISB1
Standby Current (Both Com'l. Ports TTL Level) CEL & CER Indust. VIH, f=fMAX Standby Current (One Port Com'l. TTL Level) CEL | CER V IH, Indust. f=fMAX Standby Current (Both Ports CMOS Level) CEL & CER VCC - 0.2V, f=0 Standby Current (One Port CMOS Level) CEL | CER VIH, f=fMAX[9] Com'l. Indust. Com'l. Indust.
ISB2
ISB3
ISB4
Shaded area contains advance information. Note: 9. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
5
PRELIMINARY
Capacitance[10]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10
CY7C027/028 CY7C037/038
Unit pF pF
AC Test Loads and Waveforms
5V 5V R1 = 893 OUTPUT C = 30 pF R2 = 347 VTH = 1.4V OUTPUT C = 30 pF RTH = 250 R1 = 893 OUTPUT C = 5 pF R2 = 347
(a) Normal Load (Load 1)
(b) Thevenin Equivalent (Load 1)
(c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig)
ALL INPUT PULSES
3.0V GND 10% 3 ns 90% 90% 10% 3 ns
AC Test Loads (Applicable to -12 only)[11]
1.00
(ns) for all -12 access times
OUTPUT C
Z0 = 50
R = 50
0.90
0.80
0.70
VTH = 1.4V
0.60
0.50
(a) Load 1 (-12 only)
0.40
0.30
0.20
0.10
0.00 0 5 10 15 20 25 30
Capacitance (pF)
(b) Load Derating Curve
Notes: 10. Tested initially and after any design or process changes that may affect these parameters. 11. Test Conditions: C = 0 pF.
6
PRELIMINARY
Switching Characteristics Over the Operating Range[12]
CY7C027/028 CY7C037/038 -12[1] Parameter READ CYCLE tRC tAA tOHA tACE[13] tDOE tLZOE[14, 15, 16] tHZOE[14, 15, 16] tLZCE[14, 15, 16] tHZCE[14, 15, 16] tPU[16] tPD[16] tABE[13] WRITE CYCLE tWC tSCE[13] tAW tHA tSA[13] tPWE tSD tHD tHZWE[15, 16] tLZWE[15, 16] tWDD[17] tDDD[17] Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Set-Up to Write Start Write Pulse Width Data Set-Up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid 3 25 20 12 10 10 0 0 10 10 0 10 3 30 25 15 12 12 0 0 12 10 0 10 3 20 15 15 0 0 15 15 0 Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down Byte Enable Access Time 0 12 12 3 10 0 15 15 3 10 3 10 0 3 12 8 3 10 3 12 12 3 15 10 3 15 15 3 20 Description Min. Max. Min. -15 Max.
CY7C027/028 CY7C037/038
-20 Min. Max. Unit ns 20 20 12 12 12 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 45 30 ns ns ns ns
Notes: 12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OI/IOH and 30-pF load capacitance. 13. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 15. Test conditions used are Load 2. 16. This parameter is guaranteed by design, but it is not production tested. 17. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
7
PRELIMINARY
Switching Characteristics Over the Operating Range[12] (continued)
CY7C027/028 CY7C037/038 -12[1] Parameter BUSY TIMING[18] tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[19] tINS tINR tSOP tSWRD tSPS tSAA BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-Up for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid
[18]
CY7C027/028 CY7C037/038
-15 Min. Max. 15 15 15 15 5 0 13 12 12 12 15 15 15 10 5 5 12 15 10 5 5 5 0 15 Min.
-20 Max. 20 20 20 17 Unit ns ns ns ns ns ns ns 20 20 20 ns ns ns ns ns ns 20 ns
Description
Min.
Max. 12 12 12 12
5 0 11
INTERRUPT TIMING
INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time 10 5 5
SEMAPHORE TIMING
Data Retention Mode
The CY7C027/028 and CY7C037/038 are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC - 0.2V. 2. CE must be kept between V CC - 0.2V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (4.5 volts).
Timing
Data Retention Mode VCC 4.5V VCC > 2.0V 4.5V tRC
V IH
CE
VCC to VCC - 0.2V
Parameter ICC DR1
Test Conditions[20] @ VCCDR = 2V
Max. 1.5
Unit mA
Notes: 18. Test conditions used are Load 1. 19. t BDD is a calculated parameter and is the greater of tWDD-tPWE (actual) or tDDD-tSD (actual). 20. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.
8
PRELIMINARY
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[21,22,23]
tRC ADDRESS tOHA DATA OUT tAA DATA VALID tOHA
CY7C027/028 CY7C037/038
PREVIOUS DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[21,24,25]
tACE tHZCE tDOE tHZOE tLZOE DATA OUT tLZCE tPU ICC CURRENT ISB tPD DATA VALID
CE and LB or UB OE
Read Cycle No. 3 (Either Port)[21,23,24,25]
tRC ADDRESS tAA UB or LB tHZCE tLZCE tABE CE tACE tLZCE DATA OUT tHZCE tOHA
Notes: 21. R/W is HIGH for read cycles. 22. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 23. OE = VIL. 24. Address valid prior to or coincident with CE transition LOW. 25. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
9
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[26,27,28,29]
tWC ADDRESS
CY7C027/028 CY7C037/038
tHZOE [32] OE tAW CE
[30,31]
tSA R/W tHZWE[32] DATA OUT NOTE 33
tPWE[29]
tHA
tLZWE NOTE 33 tSD tHD
DATA IN
Write Cycle No. 2: CE Controlled Timing[26,27,28,34]
tWC ADDRESS tAW CE
[30,31]
tSA R/W
tSCE
tHA
tSD DATA IN
tHD
Notes: 26. R/W must be HIGH during all address transitions. 27. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 28. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 29. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 30. To access RAM, CE = VIL, SEM = VIH. 31. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 32. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 33. During this period, the I/O pins are in the output state, and input signals must not be applied. 34. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
10
PRELIMINARY
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[35]
tSAA A 0-A 2 VALID ADRESS tAW SEM tSCE tSD I/O0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE DATA IN VALID tPWE tHD tHA tSOP VALID ADRESS tACE
CY7C027/028 CY7C037/038
tOHA
DATA OUT VALID
Timing Diagram of Semaphore Contention[36,37,38]
A0L -A 2L
MATCH
R/WL SEM L tSPS A 0R -A 2R MATCH
R/WR SEM R
Notes: 35. CE = HIGH for the duration of the above timing (both write and read cycle). 36. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 37. Semaphores are reset (available to both ports) at cycle start. 38. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
11
PRELIMINARY
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[39]
tWC ADDRESSR R/WR MATCH tPWE
CY7C027/028 CY7C037/038
tSD DATA IN R tPS ADDRESSL MATCH tBLA BUSY L tDDD DATA OUTL tWDD VALID
tHD
tBHA tBDD
VALID
Write Timing with Busy Input (M/S=LOW)
R/W tWB tPWE
BUSY
tWH
Note: 39. CEL = CER = LOW.
12
PRELIMINARY
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[40] CELValid First:
ADDRESS L,R CEL tPS CER tBLC BUSYR tBHC ADDRESS MATCH
CY7C027/028 CY7C037/038
CER Valid First:
ADDRESS L,R CER tPS CE L tBLC BUSY L tBHC ADDRESS MATCH
Busy Timing Diagram No. 2 (Address Arbitration)[40] Left Address Valid First:
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESSR tBLA BUSY R tBHA ADDRESS MISMATCH
Right Address Valid First:
tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSY L tBHA ADDRESS MISMATCH
Note: 40. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
13
PRELIMINARY
Switching Waveforms (continued)
Interrupt Timing Diagrams Left Side Sets INTR:
ADDRESSL CE L R/W L INT R tINS [42]
CY7C027/028 CY7C037/038
tWC WRITE 7FFF (FFFF for CY7C028/38) tHA[41]
Right Side Clears INTR:
ADDRESSR CE R tINR [42] R/WR OE R INTR
tRC READ 7FFF (FFFF for CY7C028/38)
Right Side Sets INT L:
tWC ADDRESSR CE R R/W R INT L tINS
[42]
WRITE 7FFE (FFFE for CY7C028/38) tHA[41]
Left Side Clears INTL:
ADDRESSR CE L tINR[42] R/W L OE L INT L
Notes: 41. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 42. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
tRC READ 7FFE (FFFE for CY7C028/38)
14
PRELIMINARY
Architecture
The CY7C027/028 and CY7C037/038 consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device.
CY7C027/028 CY7C037/038
tion). If both ports' CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C027/028 and CY7C037/038 provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
Functional Description
Write Operation Data must be set up for a duration of t SD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (7FFF for the CY7C027/37, FFFF for the CY7C028/38) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027/37, FFFE for the CY7C028/38) is the mailbox for the left port. When one port writes to the other port's mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port's mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin. The operation of the interrupts and their interaction with Busy is summarized in Table 2. Busy The CY7C027/028 and CY7C037/038 provide on-chip arbitration to resolve simultaneous memory location access (conten-
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PRELIMINARY
Table 1. Non-Contending Read/Write Inputs CE H X L L L L L L X H X H X L L X X R/W X X L L L H H H X H H OE X X X X X L L L H L L X X X X UB X H L H L L H L X X H X H L X LB X H H L L H L L X X H X H X L SEM H H H H H H H H X L L L L L L I/O 9-I/O17 High Z High Z Data In High Z Data In Data Out High Z Data Out High Z Data Out Data Out Data In Data In Outputs I/O0-I/O8 High Z High Z High Z Data In Data In High Z Data Out Data Out High Z Data Out Data Out Data In Data In
CY7C027/028 CY7C037/038
Operation Deselected: Power-Down Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Semaphore Flag Read Data in Semaphore Flag Write D IN0 into Semaphore Flag Write D IN0 into Semaphore Flag Not Allowed Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[43] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X X CEL L X X L OEL X X X L A0L-14L 7FFF X X 7FFE INTL X X L[44] H
[45]
Right Port R/WR X X L X CER X L L X OE R X L X X A0R-14R X 7FFF 7FFE X INTR L[45] H[44] X X
Table 3. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0-I/O17 Left I/O0-I/O17 Right 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left Port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free Status
Notes: 43. A0L-15L and A0R-15R, FFFF/FFFE for the CY7C028/038. 44. If BUSYR=L, then no change. 45. If BUSYL=L, then no change.
16
PRELIMINARY
Ordering Information
32K x16 Asynchronous Dual-Port SRAM Speed (ns) 12[1] 15 20 Ordering Code CY7C027-12AC CY7C027-15AC CY7C027-15AI CY7C027-20AC CY7C027-20AI
Shaded area contains advance information.
CY7C027/028 CY7C037/038
Package Name A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
Operating Range Commercial Commercial Industrial Commercial Industrial
64K x16 Asynchronous Dual-Port SRAM Speed (ns) 12[1] 15 20 Ordering Code CY7C028-12AC CY7C028-15AC CY7C028-15AI CY7C028-20AC CY7C028-20AI
Shaded area contains advance information.
Package Name A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
Operating Range Commercial Commercial Industrial Commercial Industrial
32K x18 Asynchronous Dual-Port SRAM Speed (ns) 12[1] 15 20 Ordering Code CY7C037-12AC CY7C037-15AC CY7C037-15AI CY7C037-20AC CY7C037-20AI
Shaded area contains advance information.
Package Name A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
Operating Range Commercial Commercial Industrial Commercial Industrial
64K x18 Asynchronous Dual-Port SRAM Speed (ns) 12[1] 15 20 Ordering Code CY7C038-12AC CY7C038-15AC CY7C038-15AI CY7C038-20AC CY7C038-20AI
Shaded area contains advance information.
Package Name A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
Operating Range Commercial Commercial Industrial Commercial Industrial
Document #: 38-00666-D
17
PRELIMINARY
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
CY7C027/028 CY7C037/038
51-85048-A
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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